1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and more particularly to a memory device having segmented row repair.
2. Description of the Related Art
Memory tests on semiconductor devices, such as random access memory (RAM) integrated circuits, e.g., DRAMs, SRAMs and the like, are typically performed by the manufacturer during production and fabrication to locate defects and failures in such devices that can occur during the manufacturing process of the semiconductor devices. Defects may be caused by a number of factors, including particle defects such as broken or shorted out columns and rows, particle contamination, or bit defects. The testing is typically performed by a memory controller or processor (or a designated processor in a multi-processor machine) which runs a testing program, often before a die containing the semiconductor device is packaged into a chip.
Random access memories are usually subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. Such testing ensures that hidden defects will not be first discovered during operational use, thereby rendering end-products unreliable.
Many semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to replace malfunctioning circuits found during testing. During the initial testing of a memory device, defective elements are repaired by replacing them with non-defective elements referred to as redundant elements. By enabling such redundant circuitry, the device need not be discarded even if it fails a particular test.
FIG. 1 illustrates in block diagram form a 256Mbit DRAM 20. DRAM 20 includes eight memory banks or arrays 22a-22h, labeled BANK&lt;0&gt; to BANK&lt;7&gt;. Each memory bank 22a-h is a 32Mbit array map 24 as illustrated in FIG. 2. The architecture of array map 24 illustrated in FIG. 2 divides array map 24 into a plurality of 256K blocks 30 (only one labeled for clarity). As shown, array map 24 includes eight vertical strips 26a-26h of the 256K blocks 30 across, labeled DQ&lt;0&gt; to DQ&lt;7&gt;, and is sixteen strips of the 256K blocks 30 high. Memory cells (not shown) in each 256K block 30 are arranged in a plurality of primary rows and redundant rows. For example, typically 512 primary rows and 4 redundant rows are provided.
Sense amplifiers 32 are provided between each row of 256K blocks 30 for sensing data stored in the memory cells therein. Wordline drivers 34 are provided on each side of each vertical strip of 256K blocks 30 for firing a wordline in each 256K block 30 associated with a specified row address. Accordingly, there will be an associated wordline and wordline driver for each row of memory cells in a 256K block 30. Thus, it should be understood that wordline driver 34 actually comprises a plurality of wordline drivers, one for each wordline.
Within each 256K block 30, the rows are designated as either an even row or an odd row. Accordingly, each wordline driver 34 will fire either a wordline associated with an odd row or an even row. FIG. 3 illustrates a single horizontal strip of 256K blocks 30 from FIG. 2. Wordline drivers 34a, 34c, 34e, 34g and 34i will fire even row wordlines, while drivers 34b, 34d, 34f and 34h will fire odd row wordlines. Thus, wordline driver 34a will fire even rows 40 in block 26a, wordline driver 34c will fire even rows 40 in blocks 26b and 26c, wordline driver 34e will fire even rows 40 in blocks 26d and 26e, wordline driver 34g will fire even rows 40 in blocks 26f and 26g, and wordline driver 34i will fire even rows 40 in block 26h. Conversely, wordline driver 34b will fire odd rows 42 in blocks 26a and 26b, wordline driver 34d will fire odd rows 42 in blocks 26c and 26d, wordline driver 34f will fire odd rows 42 in blocks 26e and 26f, and wordline driver 34h will fire odd rows 42 in blocks 26g and 26h.
A memory cell is accessed by applying a specific row address to the wordline drivers 34. A local wordline driver is driven by application of the address and a phase term provided from a global wordline driver (not shown) to activate the selected cell row via one of the row lines, while a column decoder (not shown) will activate the column select circuits to access specified memory cells on an open row. Accordingly, the selected row will be activated across all eight vertical strips 26a-26h.
As noted above, memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire column or row of redundant memory cells can be substituted therefore. Substitution of one or more of the spare rows or columns is conventionally accomplished by opening a specific combination of fuses (not shown) or closing antifuses in one of several fuse banks (not shown) on the die. A selected combination of fuses arc blown to provide an address equal to the address of the defective cell. For example, if the defective cell has an eight-bit binary address of 11011011, then the third and sixth fuses in a set of eight fuses within one of several fuse banks will be blown, thereby storing this address. A compare circuit (not shown) compares each incoming address to the blown fuse addresses stored in the fuse banks to determine whether the incoming address matches with one of the blown fuse addresses. If the compare circuit determines a match, then it outputs a match signal (typically one bit). In response thereto, the wordline drivers 34 of a redundant row will be activated to access the redundant row in substitution for the row with the defective memory cell.
There are drawbacks, however, with the redundant row substitution approach described above. The redundant rows of memory cells necessarily occupy space on the die. Therefore, it is desirable to obtain the maximum number of repairs using a minimum number of spare rows by utilizing a single bit repair method. This is not possible, however, when a complete redundant row must be substituted for a primary row that has only a single defective memory cell, as a substantial amount of non-defective memory cells will also necessarily be replaced by the redundant row. For example, if vertical strip 26d of FIG. 3 has a defective memory cell, when a redundant row is used to replace the row in which the defective memory cell is located, the entire redundant row will be utilized across all strips 26a-26h, even though there may be no defects in the corresponding row in the other seven strips 26a-26c and 26e 26h.
Thus, there exists a need for a memory device in which efficient use of a redundant circuit to replace a defective primary circuit is provided, thereby minimizing die space required for the redundant circuit.